Principal Engineer ASIC/FPGA
Firstpass Engineering - Phoenix, AZ

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This position is for an experienced engineer responsible for the design and/or verification of ASICs and FPGAs. The position being filled is either for the FirstPass Engineering Design Center located in Phoenix, Arizona or in Castle Rock, CO.

FirstPass Engineering designs complex ASICs and FPGAs for many well known companies in commercial, military and aerospace industries. We've been a part of the high tech industry since 1993. Current programs include satellite communications, military and commercial flight controls and supercomputer development. You’ll have the opportunity to work on a wide variety of projects and skills in a great work environment!

Candidates must have a strong working knowledge in either design or verification aspects of ASIC/FPGA development; however preference will be given to candidates who demonstrate strengths in both disciplines.

This individual is expected to drive projects to completion with minimal management oversight and guidance.

ASIC/FPGA Design Skills

- Conceptual design, including high level architecture and design partitioning
- Generation of device level requirements, micro-architecture and detailed design (technical descriptions, diagrams, drawings, etc)
- Practical experience with common design elements
- Standard internal structures (pipelining, FIFOs and memories, state machines, etc)

  • SoC embedded processor solutions
  • Macro cells (PLLs, DSP functions, SERDES, embedded hard/soft IP)
  • Industry standard interfaces (PCI, PCIe, SRIO, DDRx, Ethernet, I2C, etc)
  • DFT structures (BIST, JTAG, boundary scan, ATPG, etc)

- RTL coding

  • Broad range of languages (VHDL, Verilog, SystemVerilog, MATLAB, etc)
  • Parsing and Linting

- Synthesis concepts

  • Constraints, design and code for synthesis and timing closure, physical synthesis

- Physical design for ASICs

  • Floorplanning, place and route, parasitic extraction, clock tree planning

- Physical design for FPGAs

  • Experience with FPGA vendor design flows and toolkits (Xilinx, Altera, etc)

- Static Timing Analysis

  • Setting up constraints and tooling
  • Timing closure analysis and techniques

- Formal equivalence

ASIC/FPGA Verification Skills

- Practical experience conceptualizing, planning, and developing complete OVM/UVM SystemVerilog test environments
- High level verification planning and test strategies
- Creation of UVM components (environments, tests, drivers, monitors, predictors, scoreboards)
- Experienced with Transaction Level Modeling and Object Oriented Programming (classes, methods, polymorphism)
- Test methods and techniques with emphasis on constrained random testing
- Coverage analysis (code, functional, assertion, etc)
- Failure signature analysis, debug and determination of root cause
- Simulator setup, licensing, scripts, etc

ASIC/FPGA Common Skills

- Experience with scripting and programming languages (TCL, Linux shell scripting, C++, Perl, etc.)
- Source control and configuration management concepts and tools (SVN, CVS, ClearCase, etc.)
- Problem reporting/tracking (Jira, Perforce, Bugzilla)
- Basic connectivity (VPN, SSH, remote X-windows/desktops)
- Comfortable in either a Windows or Linux environment
- Experience working in a lab environment characterizing and debugging ASICs/FPGAs

Basic Qualifications

- 6+ years of experience in ASIC/FPGA design and/or verification
- Bachelor's degree or higher in Electrical Engineering or related
- Excellent written and verbal communication skills
- Skilled at interfacing directly with external customers and vendors
- U.S. Citizen or Permanent Resident Alien


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About this company
FirstPass provides customers with high-quality, responsive subcontract IC design services. Whether to perform turnkey designs or merely to...