R2 Semiconductor is a Bay Area Start-up Fabless Semiconductor Company currently in stealth mode seeking a Digital Design Verification Lead for mixed signal chips. The company is developing a disruptive power management technology for the Consumer Electronics space. The Company was started December 2008 and is funded by top tier Venture Capital firms: Morgenthaler Ventures, Sequoia Capital, Sigma Partners, and Third Point Ventures. The team is lead by industry veterans with 30+ years experience who have worked together over 20 years. The members of this founding team have a solid history of creating a start-up fabless semi venture, building the company, and piloting the company to a successful liquidity event. The company and position are located in Sunnyvale, CA.
The position will be responsible for all digital design verification at R2 Semiconductor. This lead role will be wholly responsible for translating the digital design requirements specification into a coverage driven testplan and then for architecting and building a SystemVerilog UVM environment to meet the plan’s requirements.
A strong background in object oriented programming (OOP) is essential. The candidate should have experience and a solid track record with building and using SystemVerilog UVM (or OVM) verification environments. The candidate should have excellent RTL debugging skills with experience using waveform and code debug tools.
The ideal candidate is a self-starter, key member leading a small fast moving design team, and is a highly motivated engineer with excellent technical, and communications skills. The position will have significant exposure to upper management with opportunity for career growth.
Responsibilities will include:
- Defining and owning the digital testplan
- Architecting and building digital verification environments SystemVerilog with UVM
- Implementing whitebox coverage and checks using SystemVerilog Assertions (SVA)
- Functional coverage implementation, analysis and closure
- Building required directed testcases
- Defining and maintaining regression running and reporting scripts
- BSEE/CE/CS with a Minimum of 4years DV experience
- Verilog and SystemVerilog expert
- Strong working knowledge of SystemVerilog's object oriented programming features
- Excellent written and oral communication skills
- Experience developing and owning detailed testplans with both directed and coverage driven testpoints
- Experience with implementing, analyzing, and closing both functional and code coverage
- Candidates with recent OVM / UVM experience are strongly preferred
- Candidates that have implemented full UVM/OVM environments (agents, drivers, monitors, coverage collectors, scoreboards) are strongly preferred
- Working knowledge of SystemVerilog Assertions (SVA)
- Solid communication and team building skills
- Self-motivated, "can-do" attitude that fits well in a start-up environment
- Experience in using Cadence design and debug tools – Incisive, Simvision
- Multiple designs in volume production
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