Education Level : Bachelor of Science degree in Electrical Engineering/ Computer Science/ Computer Engineering from an ABET accredited university. Master's Degree in Electrical Engineering is a plus.
The Powertrain System Cost Engineer ED&D
Powertrain Controls (Engineering Design & Development) analyst will be responsible for determining market competitive compensation to the supply base for a variety of Software changes including: Engine, Transmission and Driveline design projects.
Responsibilities will include understanding the tasks associated with the designing and developing a Powertrain component.
The ideal candidate will be able to evaluate the submitted costs for a Powertrain Control component involving Circuit design and signal.
Must have experience in the following skill set logic design, logic synthesis, behavioral and RTL coding using Verilog or VHDL, timing analysis, memory BIST, computer architecture, DFT, and LVS.
In addition, knowledge of signal processing and analog IC design, Performing ASIC design, verification, testing, and implementation as part of design flow for high -performance mixed-signal and RF integrated circuits (ICs).
Design and develop logic blocks in RTL and perform verification using simulation software.
Perform logic synthesis using Design Compiler and Cadence Encounter.
Write behavioral and RTL coding using Verilog or VHDL.
Perform test development, simulation, debugging, system bring up and system validation.
Verify changes by writing test cases and modify test benches to work with internal simulation environment.
Develop and simulate test benches to verify ASIC models using Verilog language.
Develop test environments for verification.
Synthesize modules from Verilog code to actual circuits.
Perform timing closure using PrimeTime static timing analysis tool, investigate timing results, and resolve timing errors.
Perform memory BIST testing and other ATE testing.
Interact with mixed-signal and RF engineers to implement calibration algorithms and work with signal processing engineers to implement digital signal processing (DSP) data paths.
Job duties require knowledge of computer architecture, DFT, and LVS.
Fundamentals of signal processing and mixed-signal IC design is desirable.
Minimum 5+ years of IC design verification experience, including mixed signal Integrated Circuits.
Proven track record of creating, evaluating, debugging, and improving verification processes
Solid experience with C. C++, Verilog and/or VHDL, as well as strong verification languages such as SystemVerilog, OVM, UVM, AVM, Vera, e, etc.
Strong scripting skills in Perl, Unix/Linux shell, TCL,etc- Matlab experience
Able to write and debug analog behavioral models in Verilog, Verilog-A, and/or Verilog-AMS.
Knowledge of signal processing and Verilog Assertions.
Ten years of automotive industry related experience
Self-starter with strong leadership skills
Demonstrated problem solving ability and project completion drive
Powertrain component familiarity
Knowledge of Powertrain components
Proficient in Microsoft Office applications (PowerPoint, Excel, Word, Outlook)
Excellent written and verbal communication skills required
Strong leadership and interpersonal skills
Strong root cause skills