P&R Sr. Engineers/Technical Managers (TTI_SJ_2013_06 and 07)
TSMC - San Jose, CA

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Job Locations: San Jose, CA or Hsinchu, Taiwan

Will be responsible for ASIC integration/implementation projects, and TSMC design methodology build-up.

MS or above in EE/CS. For Sr. Engineer positions, must have 5-10+ years of related experience. For manager positions, 10~15+ years of chip physical implementation experience. Be an expert in ASIC RTL-to-GDS design flow. Fluent with Synopsys/Cadence Synthesis/APR tools/flows. Skilled in Tcl/Perl utility program coding. Experienced with TSMC 40nm technology. Experienced in chip integration and signoff. Proven record in multi-million gate design production tapeouts. Innovative in APR design methodology. Experienced in any of the following is a plus:
- TSMC 28nm technology
- Mobile application processor’s eCPU/eGPU implementation
- Low-power implementation methodology
- Application processor implementation
- Advanced timing methodology

Other Requirements:
Must be service driven and able to interface with customer on specs/signoff/job scope discussion. Must have good communication skills, and can take tapeout pressure and work independently.

TSMC Technology is an Equal Opportunity Employer.

To learn more about us, please visit www.tsmc.com.

Important: please include the job # on the subject line of your email when sending in your resume.

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