ASIC Design Engineer
Marvell - Santa Clara, CA

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EE or CE Junior or Senior

Description:
The Intern will have the opportunity to join the fastest growing R&D group in Marvell developing
pushing-edge SOCs for high-definition video entertainment systems!

Responsibilities:
As an ASIC design engineer contributing to the complete VLSI solutions for system-on-
chip (SoC) projects.

Including developing Synthesis using Synopsys DC/DC-G, formal verification using Synopsys Formality
and Candence Verplex LEC, static timing closure and signal integrity using
Synopsys Primetime, Static power and leakage analysis using Apache, and understanding
PnR/Integration/tapeout flow, and strong PERL & TCL programming capability.

Requirements:
- Be able to resolve issues independently.
- Strong logic Design and verification knowledge with understanding on pad ring and pin mux.
- Strong understanding of ASIC design flows.
- Understanding PnR/Integration/taepout flow.
- Proficient in Perl, tcl, and shell programming.

Profession:
Engineering - Hardware

Discipline:
Digital IC Design

Marvell - 21 months ago - save job - copy to clipboard
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Thou marvell'st at my words, but be thee still; Marvell Technology Group offers digital and mixed-signal integrated circuits for data...