ASIC Design Engineer
Marvell - Santa Clara, CA

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Attitude, Understanding the flow & concept of work
BSEE with 2 years experience; MSEE or PhD preferred.

Description:
Looking for entry level engineer who can help following area.

Synthesis/STA (EDA tool : DC/PrimeTime/PTPX/…)
· Die size estimation
· Should understand each command and constraints
· Review the un-clocked F/Fs and communicate with designer in order to fix it
· Vector or Vector-free power estimation
· Can analyze the reports, find the root cause of violations and how to fix it
(This should include CTS tree skew analysis)
DFT(EDA tool : DC/TestKompress/….)
· Scan/EDT insertion including fixing Scan DRC violation
· Stuck-At, PLL/bypass PLL TDF ATPG/Test pattern generation/Verification
· Scan Failure Analysis
LEC(EDA tool : Conformal-LEC/Formality/…)
· run RTL2G/G2G formal and debug
· Review unmapped/Unreachable points
P&R interface (EDA tool : ICC/Astro/Magma/…)
Familiar with PERL/TCL is a plus.
Profession:
Engineering - Hardware
Discipline:
Digital IC Design

Marvell - 12 months ago - save job - block
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Thou marvell'st at my words, but be thee still; Marvell Technology Group offers digital and mixed-signal integrated circuits for data...