ASIC Emulation Verification Engineer
Formalized Design, Inc. - Austin, TX

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Are you looking for a contract position that will utilize your ASIC Emulation Verification expertise Do you have a strong background in SoC Designs and RTL debugging FDI has an immediate need in Austin TX that we would like to discuss with you If you are interested in applying please reply to logancallananatteberyformalizedcom mailtologancallananatteberyformalizedcom AVAILABLE NOW ASIC Emulation Verification Engineer Mentor Veloce Emulation Environment Location Austin TX Contract Length 12 Months Primary Focus Validating and debugging ASIC RTL code in a Mentor Veloce Emulation Environment Developing systemlevel tests using synthesized Synopsis VCS code to debug Developing test cases that use Debussy Debug (for Wave Verification) RTL code debug (manual eyeballing) to root cause issues with complex designs Create concurrent test cases Required Skills 6+ years of ASIC emulation 5+ years Synopsis VCS synthesis script writing 7+ years debugging RTL code Waveform check using Debussy 5+ years Novus Debussy Debug Bachelors or Masters in Electrical Engineering Computer Engineering or Computer Science If you are interested in learning more we would like the opportunity to discuss this with you in greater detail Formalized Design Inc Works Directly With the Hiring Manager How to Apply Resumes can be sent to logancallananatteberyformalizedcom mailtologancallananatteberyformalizedcom Thank you 7193218256 wwwformalizedcom ASIC / Verification / Emulation / VCS / Mentor / Veloce / Debussy / Debug / RTL
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