-Knowledge of physical layer designs for one or more of the following high-speed interfaces: PCI-Express, DP, HDMI, USB2.0, USB3.0, Faber Channel, High Speed Serial Links at 1~12 Gbps, Clock and Data Recovery (CDR) Architectures and circuits for Ethernet applications. 10Gbs and 20Gbs design experiences are highly preferred.
Knowledge of , VCO, PLL, DLL, CDR, equalizers, DFE and high-speed transceivers design are highly preferred.
High-Speed IO transceiver design
-Experience designing op-amps, band gaps, differential amplifiers
-In Depth knowledge of analog IC design
- Extensive knowledge and experience in using Cadence
- In-depth knowledge of full-custom high-speed analog layout techniques and ability to work closely with layout engineers, including directing and reviewing their work.
- Understanding of signal integrity issues in high speed wireline design.
- Understanding of process effects on designs and layout.
PhD is preferred
NXP Semiconductors has a full menu of chips to choose from. The one-time semiconductor unit of Philips is one of the largest chip makers in...