There is currently an urgent need for a Design Engineer with strong digital IC design experience to join a stable, growing organization on a full-time basis. This is a terrific opportunity offering lucrative base salaries, great benefits packages and other terrific perks.
- L ead a small digital design team from defining module level architecture specifications, performing RTL design, synthesis, timing closure and verification for next generation Mixed-Signal products.
All candidates MUST have the following experiences to qualify for consideration
- Please DO NOT APPLY unless you have a BS in EE ( MS or higher would be preferred) and a minimum of 5 years of sub-micron digital/mixed signal circuit design at 130 nm or less
- Experience with multi-million gate IC design
- Well-versed in using low-power techniques
- Experience with entire design cycle including micro-architecture specification definition, verilog coding, synthesis and timing closure to post-silicon debug and support in lab environment.
- Strong language user in SystemVerilog, Verilog, Perl, Unix Shell.
- Experience in both RTL and gate level verification and debug.
- Experience in coverage based/random test environment and assertion generation.
- Experience in Cadence design environment is a plus.
If interested and QUALIFIED , please send resume in Microsoft Word format to:
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