Engineer, ASIC Design
Marvell - Aliso Viejo, CA

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Master degree in Electrical Engineering or related technical field. Must have the following skill set (as evidenced by experience or graduate-level coursework): Verilog, System Verilog, Tcl, PrimeTime, digital circuit design, timing analysis, Cadence Encounter, C programming, design for test, low power design, Cadence Virtuoso, RTL design, and place and route. Must pass company technical review.

Multiple openings available. Perform ASIC (Application Specific Integrated Circuit) design, verification, testing, and implementation. Design and develop logic blocks in RTL and perform verification using simulation software, including VCS and Verdi. Perform test development, simulation, debugging, system bring up and system validation. Verify changes by writing test cases and modify test benches to work with internal simulation environment. Develop and simulate test benches to verify ASIC models using Verilog language. Develop test environments for verification.Synthesize modules from Verilog codes to actual circuits. Perform timing closure using PrimeTime static timing analysis tool, investigate timing results, and resolve timing errors. Perform memory BIST testing and other ATE testing. Job duties include the utilization of Design Compiler, Cadence Encounter, and require knowledge of computer architecture.

Engineering - Hardware

Hardware Design

Marvell - 19 months ago - save job - copy to clipboard
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Thou marvell'st at my words, but be thee still; Marvell Technology Group offers digital and mixed-signal integrated circuits for data...