Engineer, Design for Test (DFT)
Marvell - Santa Clara, CA

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  • Hands on DFT experience including boundary scan, memory BIST, scan, BIST, 3rd party IP integration, at-speed and IDDQ tests, ATPG, and fault simulation.
  • Experience with ATE pattern bringup and volume production preferred.
  • Expertise with DFT tools from Synopsys, Mentor Graphics, Syntest, and Logic Vision.
  • Strong logic Design and verification background with experience in STA.
  • Proficient in Perl, tcl, and shell programming
  • BSEE (MSEE preferred) with 3 years direct related experience in specification and implementation of DFT.
Description:
As a DFT engineer contributing to the complete DFT solutions for system-on-chip (SOC) projects.
Including developing DFT architecture, writing test plan, implementing DFT infrastructure, generating structural and functional test vectors, and working with test engineer to bring up test vectors on tester. And support for mass production.

Profession:
Engineering - Hardware

Discipline:
Hardware Design

Marvell - 2 years ago - save job - copy to clipboard - block
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Thou marvell'st at my words, but be thee still; Marvell Technology Group offers digital and mixed-signal integrated circuits for data...