Engineer, Senior Design for Test
Marvell 8 reviews - Santa Clara, CA

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• At least a B.S. degree in EE or CS, M.S. preferred, with 2 or more years of relevant industry experience.
• Knowledge of DFT architecture including SCAN, MBIST and JTAG is desired.
• Knowledge of various industry standard DFT and design tools is desired but not required.
• Experience with Verilog modeling, simulation and debug.
• Experience with scripting languages like Perl and TCL.
• Experience with test-bench development using Verilog or System Verilog.
• Must be self-motivated and creative with strong problem-solving skills.
• Should be flexible, adaptable and work well in a team environment with good verbal and written communication skills

Good at c code for ARM, master different tools set for ARM (IAR, RVDS, openocd)
Familar with ARM SOC

• Verification of Design-For-Test (DFT) features including scan, at-speed test, MBIST, IEEE 1500, JTAG, I/O loopback and boundary scan for a highly integrated SoC.
• Develop test plans and Verification infrastructure like testbenches, stimulus, checkers and scripts.
• Ensure overall functionality, pre tape-out, of the SoC in its targeted application.
• Support gate level verification, run regressions, manage bug tracking, analyze code & functional coverage.
• Provide silicon bring-up support and debug.
• Be a solid member of a small dynamic team where you can contribute in many technical areas.

Engineering - Hardware

Digital IC Design

About this company
8 reviews
Thou marvell'st at my words, but be thee still; Marvell Technology Group offers digital and mixed-signal integrated circuits for data...