Engineer, Senior Digital IC design
Marvell - Santa Clara, CA

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MS in EE with 3+ years communications/DSP IC experience.
BS in EE. with 4+ years communications/DSP IC experience

Understanding ASIC design flow.
Good Understanding of DSP and communications algorithms, and DSP system design specification.
Experience in micro-architecture design, RTL coding, and functional verification.
Proficient in design and verification tools.
Good understanding of synchronous/asynchronous design, and timing requirement for complicate DSP modules.
Experience in chip bring up and validation
Experience in system Verilog is a plus.

As a member of wireless base band design team, you will be involved in many stages of base band processor chip development. Your responsibilities include, but not limited to:
• block level micro-architecture design, RTL coding, verifications, and documentation.
• verification environment development and chip level verification planning and execution.
• Block and chip level synthesis, timing clusure and formal verification.
• Chip bring-up and validation support.
Engineering - Hardware
Digital IC Design

Marvell - 19 months ago - save job - block
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Thou marvell'st at my words, but be thee still; Marvell Technology Group offers digital and mixed-signal integrated circuits for data...