Engineer, Senior Staff ASIC Design
Marvell - Boise, ID

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BSEE with 2+ years experience or MSEE with focus in ASIC physical design including:
Full chip floorplanning, place & route, physical verification.
Static timing analysis and timing closure, signal integrity.
Experience in clock and power implementation methodologies and practices in low power designs.
Understanding of hierarchical/timing driven layout methodologies and practices.
Circuit level comprehension of critical paths. Spice experience a plus.
Prefer experience with ICC, Primetime, Design Compiler and Calibre.
Automation experience with scripting languages (Perl, TCL, Makefile etc.)

Description:
Candidate will perform physical design of complex, low power SOC ASICs in 40nm, 28nm and smaller processes.
Major responsibilities will include but are not limited to:
Floorplanning and hierarchical partitioning.
Hierarchical and timing driven place & route.
Parasitic extraction and static timing analysis.
Power and noise analysis, clock tree analysis, signal integrity analysis.
Physical verification.
Work with designers to resolve problems and implement ECO requests.

Profession:
Engineering - Hardware

Discipline:
Digital IC Design

About this company
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Thou marvell'st at my words, but be thee still; Marvell Technology Group offers digital and mixed-signal integrated circuits for data...