Engineer, Senior Staff ASIC Design
Marvell - Santa Clara, CA

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MSEE with 5+ years of experience/PhD with working knowledge in following areas preferred:

- Good understanding of DSP and communication building blocks
- Bluetooth, or other wireless baseband design/implementation experience
- Hand on lab experience to bringing up silicon sample
- Micro-architecture specification and verilog RTL coding
- Familiar with ASIC implementation flow: synthesis(DC), DFT, timing closure(PT-SI), and formal verification
- Verification test bench development
- Excellent communication skills

Experience in following areas a plus:

- Matlab, C/C++, Perl, shell script, or TCL.
- System Verilog/VMM
- Interfacing with physical designer for floor planning/power optimization/CTS/post layout timing closure.
- Mix signal and low power design.
- Complete product cycle experience from specification to production

Description:
The candidate will work as staff design engineer for wireless/communication ASICs development. The
main responsibilities includes for IP delivery and silicon validation support. The candidate may be
working full ASIC design cycle from design, RTL coding, verification, synthesis, timing closure,
DFT, backend support and silicon bring-up.

We are the most innovative company working in the semiconductor industry with an outstanding
history of delivering next generation products. Come join us and work with a dynamic and motivated
team to address exciting opportunities in the areas of wireless communication.

Profession:
Engineering - Hardware

Discipline:
Digital IC Design

About this company
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Thou marvell'st at my words, but be thee still; Marvell Technology Group offers digital and mixed-signal integrated circuits for data...