Requirements:MS in Electrical Engineering or related field with 3+ years of experience in back-end ASIC development. Experience in physical synthesis and timing analysis. Experience with the following back-end ASIC development tools: Synopsys (Design Compiler, Physical Compiler, PrimeTime, PrimeTime-SI), Cadence (Conformal LEC, NC-Sim)
Description:
Candidate will perform back-end ASIC development tasks on complex SOC ASICs. Responsibilities include Top Level RTL design, physical synthesis, ...
Marvell - 30+ days ago
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