• 4+ years experience in Physical Design of ASICs
• 4+ years experience in Full Chip Integration
• 4+ years experience in Full Chip Post Place And Route
• Hands-on experience in physical design of large ASICs
• Extensive experience in clock and power implementation methodologies and practices in low power designs
• Deep understanding of hierarchical/timing driven layout methodologies and practices
• Experience with design and integration of hardened IP modules
• Experience in timing closure, signal integrity and physical verification
• Ability to collaborate with RTL, synthesis, STA engineers in timing closure, gate level verification and debug
• Circuit level comprehension of critical paths. Spice experience a plus.
• Proven expertise with Synopsys tool suites (or equivalent)
• Prefer experience with ICC, Primetime, Design Compiler and Calibre
• Automation experience with scripting languages (Perl, TCL, Makefile etc.)
• BSEE required, MSEE preferred
Candidate will perform physical design of complex, low power SOC ASICs in 40nm, 28nm and smaller processes.
Major responsibilities will include, but not limited to:
• Floorplanning and hierarchical partitioning
• Hierarchical and timing driven place-and-route
• Parasitic Extraction and Static Timing Analysis
• Power and Noise analysis, clock tree analysis, and signal integrity analysis
• Physical Verification
• Work with Designers to resolve problems and implement ECO requests.
Engineering - Hardware
Digital IC Design
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