Engineer, Staff ASIC Design
Marvell - Santa Clara, CA

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* BS or MS in Electrical Engineering and 5+ years of working experience
* Familiar with ASIC design and verification methodologies and flows
* Experience in the usage of state-of-the-art design tools
* Proficient in behavioral and RTL coding, Verilog preferred
* Experience in logic synthesis, timing closure and DFT (Design For Test)
* Proficient in TCL/Perl script language
* Strong verbal and written communication skills and proactive team-work spirit
* Direct design experience in high speed SERDES PHY such as SATA, SAS, FC (Fibre Channel), PCIe, USB3, and USB2 is a plus
* Familiarity with physical design flow is a plus

Description:
The candidate will be responsible for design and verification of high-speed and low power digital circuits using state-of-the-art IC design methodologies and flows, which include architecture specification, multi-clock domain RTL design and verification, synthesis, static timing analysis, DFT (Design for Test) and SCAN pattern generation, chip integration, and post silicon debugging. It also requires the candidate to interface with the physical designer to oversee and guide layout activities. The CMOS technology is from 55nm down to 20nm. Knowledge of high speed serial transceiver (SerDes) with the speed from 1Gbps up to 50Gbps such as SATA, SAS, FC (Fibre Channel), PCIe, USB3, and USB2 is a plus.

Profession:
Engineering - Hardware

Discipline:
Digital IC Design

Marvell - 20 months ago - save job - copy to clipboard
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