Engineer, Staff ASIC Design
Marvell - Santa Clara, CA

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Looking for the candidate who is familiar with digital IC design methodologies, understands all stages of ASIC design flows, and is experienced with state-of-the-art design tools. The candidate is strong in logic design and verification, and has solid knowledge of related VLSI architectures. Minimum requirements:
  • Knowledge of HDL and experience in behavioral and RTL coding, Verilog preferred.
  • Knowledge of logic synthesis and timing analysis.
  • Knowledge of SCAN.
  • knowledge of ATPG will be plus.
  • BS in Electrical Engineering/Computer Engineering. MSEE or PhD preferred
The Data Storage SOC Mobile is exciting, rewarding and dynamic, with many opportunities for professional growth for a motivated candidate. As part of Marvell's Data Storage division we develop and implement the leading edge System-on-Chip solutions. You work closely with your peers, test engineers, field application engineers and product engineers to find the optimal and most cost efficient solution for our customers. Responsibilities Design and integrate IPs for System-on-Chip solution using state-of-the-art IC design methodologies and design flows.
  • Perform RTL coding.
  • Perform functional verification of design on block and system level.
  • Perform synthesis and timing closure.
  • Perform ATPG pattern generation.
  • Provide design documentation, description and information to application engineers, field application engineers, test engineers, production engineers and customers
Engineering - Hardware

Digital Circuit Design

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Thou marvell'st at my words, but be thee still; Marvell Technology Group offers digital and mixed-signal integrated circuits for data...