Engineer, Staff Design
Marvell - Aliso Viejo, CA

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Prefer BS or MS with five to eight years experience in ASIC development, particularly integration of multiple IP's into an SOC implementation. Looking for people skilled in deep sub-micron ASIC timing closure flow including Prime Time-SI, Cross-Talk analysis tools, Power Analysis tools, Test insertion tools such as Tetramax, or DFT Max.

Work on the top level of an SoC design.
Participate in the integration of multiple IP's, the definition of pin out, testability, and synthesis requirements.
Leverage the latest tools to develop floor plans.
Analyze deep sub-micron timing using latest techniques to account for cross-talk and the effects of IR voltage drop.
Be a primary interface between the logic design team and the place and route team.
Help to turn a design into a product.

Engineering - Hardware

Digital IC Design

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Thou marvell'st at my words, but be thee still; Marvell Technology Group offers digital and mixed-signal integrated circuits for data...