Engineer, Staff Design
Marvell 3.88 reviews - Santa Clara, CA

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Main Responsibilities:
+ Develop testbench for full chip and block level verification of Mobility product(s).
+ Architect and Develop verification environment using UVM, OVM
+ Develop testbench for verifying Low-Power techniques like, Power Gating, Power Scaling,
Power-Up/Down sequencing.
+ Develop test plans, execute and track progress

+ Self Motivated, Team Player that can work with various groups
+ Ability to multi-task various verification activities.
+ BS in Electrical Engineering required, prefer MS Electrical Engineering or Computer Science
+ 5+ years in ASIC verification. Experience in building Verification environments using
SystemVerilog, VMM/OVM
+ Past experience in Low-power verification is a huge plus
+ Developed CPF/UPF flow and specification
+ Experience building verification environment using Constraint Random
+ Strong knowledge of ARM, AXI, APB, DMA, DDR[2/3] controllers
+ Familiar with peripheral devices like I2C, SDIO, USB, SDRAM, USIM
+ Prior experience in verifying OFDM[A]/DMT based systems, digital modems, GSM/GPS/CDMA, Ethernet
Physical Layer or other communication systems would be helpful but not required
+ Should be comfortable with developing/modifying C/C++, Shell scripting, Perl, and Makefiles


Come be part of the dynamic environment at Marvell. As a technical contributor you will be
part of the team developing Next Generation of Broadband Wireless Products.

Engineering - System

System Engineering

About this company
3.88 reviews
Thou marvell'st at my words, but be thee still; Marvell Technology Group offers digital and mixed-signal integrated circuits for data...