Engineer, Staff Design for Test
Marvell - Santa Clara, CA

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BSEE, MSEE preferred with at least 5 years of experience in EDA or ASIC design with emphasis on DFT work.
In-depth knowledge of DFT: scan, memory BIST, logic BIST, boundary scan, JTAG.
In-depth knowledge of ATPG, pattern simulation and tester-related debugging/diagnosis.

Experience with Synopsys DFTC/TetraMax or Mentor fastscan/TestKompress and scan compression.
Familiarity with the ASIC design flow: synthesis, timing closure, low power, delay calculation, etc...
Familiarity with ASIC libraries such as Liberty, Verilog, Volcano, and MilkyWay.
UNIX OS: Solaris and Linux RedHat. Version control tools. Scripting languages such as Tcl and Perl. C/C++ desirable but not required.
Clear verbal and correct written communication skills.
Collaborative interaction with teammates and design teams.

- Support: Support various local and remote design teams with DFT activities and EDA tools. Tools cover all DFT products from all EDA suppliers such as Synopsys, Mentor, Syntest, Cadence, etc...
- Design Services: Execute various DFT flows (SCAN, ATPG, BIST, JTAG, Simulation, etc..) for design teams to help them complete tapeouts.
- Tool Evaluations: Evaluate and compare DFT tools and make appropriate recommendations to management.
- R&D: Develop scripts/programs, flows and methodologies to automate and improve design productivity. Develop and publish application notes as needed.

Engineering - Hardware

Hardware Design

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Thou marvell'st at my words, but be thee still; Marvell Technology Group offers digital and mixed-signal integrated circuits for data...