BS/MS in EE/CS with 5+ years of hands-on experience in CAD back-end physical design and verification. Familiar with hierarchical physical design strategies, methodologies and deep sub-micron technology issues. Familiar with ASIC design flow, Verilog HDL, synthesis and timing closure.
• Successfully track records of taping out complex SOC chips.
• Programming-minded, solid coding experience in Makefile/Tcl/Tk/Perl.
• Self-motivated team worker, good verbal and written communication skills.
• Must be a power user of either Synopsys suite (Astro, Apollo, JupiterXT, Physical Compiler, IC Compiler), Magma suite (BlastFusion, BlastPlan), or Cadence suite (First Encounter, Nanoroute).
• Solid knowledge on static timing analysis (PrimeTime), EM/IR-Drop/crosstalk analysis (Celtic, PTSI, Apache, AstroRail), formal or physical verification (Formality, Verplex, Calibre, Hercules) a plus.
As a key member of central physical design team, you will provide backend design service for multiple Marvell design groups, from floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna) to backend project management. You will have the opportunity to work on many varieties of challenging designs, i.e. low power and high speed SOCs. You will work closely with frontend and integration team to ensure successful tapeouts.
Engineering - Hardware
Thou marvell'st at my words, but be thee still; Marvell Technology Group offers digital and mixed-signal integrated circuits for data...