Engineer, Verification Design
Marvell - Santa Clara, CA

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BS w/ 2 year of logic front-end design experience
4 year experience preferred
or MS in electrical engineering, computer science or equivalent.

Description:
Must have exposure to logic design experience using Verilog, RTL simulation, STA, timing fix, lint and versioncontrol.
Srong in documentation and presentation.
Indepth understanding of processor pipeline architecture, memory sub-system, cache system. Instruction set architecture.
Must have taken computer architecture courses.
Good team work spirit and communication skill.
Willing to learn.
Description: ASIC design engineer Focus on logic implementation of algorithms, control modules and SoC integration.

Profession:
Engineering - Hardware

Discipline:
Design Verification

Marvell - 17 months ago - save job - copy to clipboard
About this company
7 reviews
Thou marvell'st at my words, but be thee still; Marvell Technology Group offers digital and mixed-signal integrated circuits for data...