BS w/ 2 year of logic front-end design experience
4 year experience preferred
or MS in electrical engineering, computer science or equivalent.
Must have exposure to logic design experience using Verilog, RTL simulation, STA, timing fix, lint and versioncontrol.
Srong in documentation and presentation.
Indepth understanding of processor pipeline architecture, memory sub-system, cache system. Instruction set architecture.
Must have taken computer architecture courses.
Good team work spirit and communication skill.
Willing to learn.
Description: ASIC design engineer Focus on logic implementation of algorithms, control modules and SoC integration.
Engineering - Hardware
Marvell - 13 months ago
Thou marvell'st at my words, but be thee still; Marvell Technology Group offers digital and mixed-signal integrated circuits for data...