Engineering, Manager
Marvell - Santa Clara, CA

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  • BSEE plus 6-8 years of experience or equivalent.
  • Good software skills in Linux/Unix utilities including:
  • Makefile creation
  • Shell scripting (c-shell, bash, etc)
  • Perl, TCL and/or Python coding
  • The candidate should be knowledgeable in ASIC design flow tools
such as:
  • VCS, NCVerilog
  • Design Compiler, RTL Compiler
  • IC Compiler, Talus or Encounter
  • GDS verification with Calibre DRC/LVS/LPE
  • Extraction tools such as StarRC/xRC
  • PrimeTime or other STA tool
  • Tool knowledge in the following areas is also desirable:
  • Hspice, Eldo, Finesim,
  • Sagantec SiClone/nMigrate/LTBX,
  • Laker, Virtuoso
  • Liberate, SiliconSmart
Experienced electronic engineer wanted for block level IP view
generation and validation, library test structure creation and library
validation. The position requires experience in flow level
verification of standard cell libraries and IP blocks including low
power extensions. The person should have an ASIC design background
with experience in 40nm or smaller technology a plus.

The candidate should be able to automate cell level/block level view
generation as well as design flow. They will be expected to drive an
increase in overall productivity in library development, IP creation
as well as IP database verification and design. They should also have
good communication skills as they will interact with multiple IP and
library developers working in a variety of designs and technology
nodes. Design enablement is expected in nodes ranging from 250nm to
14nm design.

Engineering - Hardware

Digital IC Design

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Thou marvell'st at my words, but be thee still; Marvell Technology Group offers digital and mixed-signal integrated circuits for data...