Primary Responsibilities...Verification environment definition...System Verilog implementation...Integration and debug of complex designs Requirements...BSEE...3-5 years experience in VLSI verification development...Experience in complex designs such as PHY and NETWORKING environments...Knowledge in System Verilog is an advantage...Familiarity with Synopsys tools is an advantage...Exceptional drive and motivational skills
VentureLoop - 2 years ago
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