Internship, Standard Cell Design
Arm Ltd - Austin, TX

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Job Description

ARM offers IC designers a wide range of choices from its broad portfolio of standard cell, memory, and I/O products. The ARM product line is optimized for each silicon technology. ARM's Process-Perfect™ Design Methodology includes comprehensive QA and validation procedures that can enable accurate designs with high manufacturing yields. ARM products have been used in circuits running as fast as 2GHz+ and are in production or development at 250nm, 180nm, 150nm, 130nm, 90nm, 65nm, 45nm, 32nm, and 28nm semiconductor processes for various foundries and IDMs.

Our circuit group is comprised of some of the industry’s leading experts in deep submicron circuit design and design for manufacturing (DFM) techniques. This position is a rare opportunity for a digital circuit professional to work with a very successful circuit and layout team. The team has exposure to a wide variety of design rules from leading edge foundries as well as design teams from many of the world’s leading developers of digital ICs making for an ideal learning environment.

Job Purpose
We are seeking a highly motivated MSEE/MSCE student to complete an internship in our Standard Cell team for two consecutive semesters. The successful candidate will be responsible for the development of standard cell libraries in a wide variety of different processes targeting all extremes of power, performance, and density. They will work as part of a small team to optimize schematics in close cooperation with the mask design team, generate all standard library views, and verify all views by exercising them using a variety of industry standard tool flows.

Accountabilities / Responsibilities
• Circuit design of standard cells including traditional logic cells as well as advanced power management cells
• Verification of functionality, performance & power of developed circuits
• Generation of all views delivered with our Physical IP product lines
• Testing of all views by exercising them in several industry standard design flows
• Understanding of layout in order to effectively work with the mask design team
• Understanding of deep submicron device physics in order to account for these non-ideal effects during cell design
• Understanding or an ability to learn a wide variety of industry standard modelling formats including: Liberty (CCS, ECSM, and NLM), Verilog, LEF, Milkyway, Spice, and CDB
Job Requirements
Essential Skills and Qualifications
• Currently pursuing a MASTER'S DEGREE in Electrical Engineering, Computer Engineering or other relevant technical discipline
• Solid understanding of MOSFET electrical characteristics
• Solid knowledge of UNIX scripting, C++/PERL
• An understanding of transistor level device physics
• Experience with transistor level design of static circuits including state retaining elements like latches and flops
• An understanding of power, performance, and area tradeoffs
• An understanding of layout at the transistor level
• Experience with transistor level circuit simulators
Desirable Skills & Experience
• An understanding of extraction methodologies and limitations
• Diagnostic skills for tools and resultant reports
• Experience with LEF and Milkyway view formats
• Experience with Synthesis, Place and Route flows
• Experience with Java, XML
Interpersonal Skills
• Ability to cooperate & communicate well with the library development team
• Motivated to continuously develop skills and accept a variety of responsibilities as part of contributing to the design center’s success
• Demonstrated positive attitude and respect for all members of the team
• Willingness to iteratively improve designs and repeatedly attempt to develop solutions to difficult problems