Company: GLOBALFOUNDRIES U.S. Inc.
Location: Malta, NY
Position Title: MTS Technology & Integration Engineer
Hours: Monday – Friday, 8:00 am to 5:00 pm
Summary of Duties: Function as part of a BEOL Process Integration engineering team participating in advance technology development and manufacturing implementation in GLOBALFOUNDRIES' state of the art 300mm wafer fab. The primary responsibility of this position is to develop and/or implement advanced process technology nodes to meet GLOBALFOUNDRIES' technology roadmap requirements. Develop middle-of-line (MOL) and back-end-of-line (BEOL) integrated process flows for 40nm and beyond foundry technologies including high-performance, general purpose and low power variants. Participate in the technology transfer activities from Fab1 in Dresden, Germany to Fab8 in Malta, NY. Work closely with yield, product, and customer engineering organizations to meet all customer technology and company cost revenue goals.
Qualifications: Requires a Bachelor’s degree in Materials Science, Physics, Engineering, Chemistry, or a related field of study and 5 years experience as a Principal Engineer or in a closely related Semiconductor process engineering role. Also requires demonstrated experience in MOL and/or BEOL integrated process modules for interconnect-to-active device Contacts and Local Interconnect schemes and for Cu / low k interconnects and their constituent unit processes, such as Cu plating, PVD/CVD deposition for contact and local interconnect metallization, Cu liner and seed and low k dielectric materials, W, Cu and low k CMP, and reactive ion etch. Fundamental understanding of unit process and integrated module interactions and their effect on electrical parametric (R-C), defectivity and manufacturability, yield and performance criteria. Experience in transferring, implementing, ramping and sustaining process technologies in a high volume foundry manufacturing setting with a focus on customer specific product/technology targeting and customization, process simplification and optimization for yield improvement and cost reduction. Strong fundamental understanding of solid state device physics, interconnect technology, and the implications of interconnect characteristics and performance on technology and product behavior. Strong capabilities in the design, execution, and analysis of experiments. Experience in advanced technology (90nm or below). Alternately, will accept a Master’s degree in Materials Science, Physics, Engineering, Chemistry, or a related field of study plus 3 years of experience as a Principal Engineer or in a closing related Semiconductor process engineering role in lieu of a Bachelor’s degree in Materials Science, Physics, Engineering, Chemistry, or a related field of study and 5 years of experience as a Principal Engineer or in a closing related Semiconductor process engineering role.