Packaging Engineer
Silicon Laboratories - Austin, TX

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This individual is responsible for all new products and packages introduce to Assembly supplier sites prior to volume production. The scope covers from design stage to full production, providing internal/external technical resolutions and customer support on engineering issues.

Responsibilities
• Establish Assembly Design Capability and Design for Manufacturing Rules and work with supplier on continuous improvement.
• Document technology and process rules for ongoing NPIs
• Conduct Package risk assessments for NTI and NPI activities
• Establish package project mitigation plans with Product and Design teams.
• Work with external suppliers to improve technology awareness and align the internal packaging roadmap.
• Review final package design per established design rules and product performance constraints
• Conduct final package release audits for each NPI.
• Conduct scheduled engineering builds and tracking for new product checkout.
• Establish and maintain database for the Package / Process Technology roadmap, Qual reports and Qual data.
• Work closely with Manufacturing Technology team to ensure product designs are done right the first time.
• Conceptualize cost down activities / projects to support the packaging's cost target.
• Review the new processes and technology of the new products with the Manufacturing and Quality teams before going to full production stage.
• Work with supplier on DOE matrix / qualification needed to achieve long term solution & ensure manufacturability of product / process.
• Handle qualification builds in support of supplier PCN, coordinating both reliability and final test.
• Conduct occasional audits / meetings to resolve issues and set out the improvement action activities at supplier’s site.
• Work with material suppliers to determine the feasibility/ assessment of potential solutions.
Education and/or Experience:
• Bachelor Degree Required. BSME, IE, or EE
• 3~4 years as Process Engineering (Phase 2) / Package Development Engineer (Phase 3) with knowledge in process and material development.
• Excellent communication skills as well as detail-oriented work ethic are required.
• Demonstrated ability to develop and implement process enhancements and improved efficiencies.
• Experience with leading Internal/External engineering teams to help resolve subcon packaging issues.
• Should have working knowledge of IC assembly, materials, testing, qualification and packaging with substrate and leadframe design background.
• Must have strong analytical and leadership skills.
• Fluent in either Korean or Mandarin is a plus.
• Proficient in CAD and Microsoft Office suite (Excel, Powerpoint, Word,)
• Must be willing to travel and spend periods of time at supplier factories if needed.

About this company
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Silicon Laboratories Inc. designs and develops mixed-signal analog intensive integrated circuits (ICs) for a range of applications. Its...