Principal Engineer
Arm Ltd - San Jose, CA

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Background:

ARM offers IC designers a wide range of choices from its broad portfolio of Artisan memory products. The Artisan high-performance, high-density, low-power and ultra low-power memory generators are optimized for each silicon technology. ARM's Artisan Process-Perfect™ Design Methodology includes comprehensive QA and validation procedures that can enable accurate designs with high manufacturing yields. ARM memory products have been used in circuits running as fast as 1GHz+ and are in production or development at 250nm, 180nm, 150nm, 130nm, 90nm, 65nm, 45nm, 32nm, 28nm, and 20nm semiconductor processes for various foundries and IDMs. Our circuit group comprises some of the industry’s leading experts in deep submicron circuit design and design for manufacturing (DFM) techniques. This position is a rare opportunity for a digital circuit professional to work with the world’s most successful circuit and layout team with exposure to a wide variety of design rules from leading edge foundries.

Role:
• Contribute in all parts of Advance Product Memory development flow, starting at design spec
• Understand Memory design and development, analysis memory marginality in advance technology (45nm and beyond)
• Understand and perform physical verification, memory characterization, FE verification, release procedure and QA flow of the memory compilers
• Experiment and evaluate new memory architectures and methodologies
• Work with key resources to continually define, improve and develop memory infrastructure and methods
• Lead and deliver on complex project requirements
• Drive multiple projects and provide necessary technical guidance to the engineers
• Perform presentations to ARM partners on memory products, product developments, memory technology
• Work with key technical staff within the division as well as other divisions within ARM
• Ensure high quality and high performance in memory compilers
Job Requirements
Essential Technical Skills:
• 12 years of relevant circuit design experience (for BSEE)
• 10 years of relevant circuit design experience (for MSEE)
• Circuit design experience with memory compilers
• Circuit/Layout experience with deep submicron technologies (90nm or smaller)
• Fundamental understanding of technology tradeoffs in deep sub-micron design
• Fundamental understanding of Design For Manufacturability (DFM) layout techniques
• Familiarity with Cadence Virtuoso (DFII, Opus) layout environment
• Experience in low power circuit techniques
Desirable Skills:
• Experience working with place & route chip design tools
• Experience with layout automation tools, such as Prolific.
• Experience with other EDA tools such as design_compiler, Physical Compiler, PrimeTime, SoC Encounter, Pacific, Nanosim, Spectre, HSPICE, etc
• Programming or scripting experience
• Coding, modifying, or reading DRC/LVS runsets
Personal Skills:
• Enthusiastic, self-motivated, and flexible
• High degree of initiative
• Willingness and ability to contribute to process improvement initiatives
• Strong communication skills, oral and written
• Excellent presentation skills and ability to “think on your feet”
• Flexibility and willingness to work with staff across the globe
• Ability to travel
Package:
• Competitive salary commensurate with experience
• Equity in the form of Restricted Share Units
• Annual bonus plan
• Health, Life and Accident Insurance
• Development opportunities
• 4 weeks vacation
• 4 week sabbatical after 4 yrs

About this company
ARM Holdings plc (ARM) designs microprocessors, physical Internet protocol (IP) and related technology and software, and sells development...