The Network Switch Group at Broadcom has introduced several leading edge networking ASICs and systems including packet processing and very high density traffic management and fabric ASICs in the L2/L3 networking space over the past decade. Bringing these complex chips to market on aggressive schedules and with first time silicon success to meet customer requirements and success requires a world class team of engineers including design as well as verification and validation experts. The process of taking a chip to production requires efficient and complete qualification and validation processes that could become a bottleneck if not tuned and managed correctly. The end-to-end verification and validation flow for ASIC's and system level implications of performance etc... is a key part of bringing a product to market and making customers successful with adoption of the technology.
The successful candidate will be responsible for various key tasks in the areas of verification of cutting edge network switch routing designs. The day-to-day tasks for this position include but are not limited to the following:
1) Participating in the verification processes of L1/L2 (PHY/MAC) subsystems within these chips
2) Understanding the architecture and implementation of these subsystems and coming up with in depth test plans for verifying various key networking features such as port configurations for various network topologies and interfaces such as 10G/40G/100G+
3) Developing verification environments including testbenches and verification API’s associated with the chip architecture to enable testing of various features within the chips as well as scripts and Makefiles as required to run the environment in various tool chains.
4) Implementing test plans into executable test suites using a cutting edge Systemverilog verification environment as well as leveraging high performance verification platforms such as testbench acceleration and In-circuit emulation as required.
5) Executing the verification process to completion pre-silicon using various functional and code coverage metrics as measures of completion
6) Participation in driver development and Lab bringup and debug highly desirable. Job Requirements The successful candidate will satisfy the following requirements:
1) MSEE or BSEE or equivalent, with concentration in digital design and excellent academic standing. Experience required is typically a BS degree and 10 years of experience, or an MS degree and 8 years.
2) Familiar with Hardware description languages (Verilog/SystemVerilog/SystemC/VHDL), high level languages (C++), scripting languages (Perl, Tcl) and Object Oriented Programming (OOP).
3) Exposure to cutting edge verification and validation techniques and methodologies using Object Oriented modular reusable environments in languages such as Systemverilog, SystemC, C/C++, Perl, TCL/TK
4) Strong understand and prior experience of end-to-end verification process from test plan definition to coverage closure on ASIC/SOC silicon that has gone into mass production
Broadcom Corporation - 2 years ago
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