Digital Design Engineer to work in Cary Analog Design Center of Cadence SOC R&D group. As a member of the team, this candidate is expected to posses the following technical skills: Logic Synthesis, Static Timing Analysis, Floorplanning, Place-and-route, Clock Tree Design, Timing Closure, Noise analysis, Low Power Design, Physical Verification. In addition to the technical skills this candidate will be expected to lead the physical design of leading edge, 10 million gate plus designs in 90nM and below technologies.
Cadence Encounter design expertise and 28nm process node experience a plus.
US Citizenship preferred, as many projects carry US restrictions
7+ years experience
Cadence is the global leader in software, hardware, and services that is driving the transformation of the electronic design automation (EDA) industry. This application-driven approach for creating, integrating, and optimizing designs helps customers realize Analog & Digital ICs , System-On-Chip devices, IP and complete systems at lower costs and with higher quality.
Cadence is an equal opportunity employer and is committed to hiring a diverse workforce.
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Cadence Design Systems - 18 months ago