The engineer will work on hardware-software automation project as part of device and timing modeling, that is responsible to create customer centric software device models from raw hardware description. The work involves understanding hardware design flow including backend implementation like schematics and layout and coming up with new solutions for timing characterization of FPGA for software timing analysis. The candidate is expected to contribute significantly on variation modeling for advanced process node and coming up with proprietary ways to handle process/voltage/temperature in software tools flow. The solutions would have a constraints of fast turnaround time for timing characterization and low disk-footprint for the data that is delivered to the software tools.
Excellentprogramming skills in C++ and algorithms.
Workingknowledge of backend timing flow including industry standard formats likeliberty and spef
Workingknowledge of static timing analysis tools and some experience withPrimeTime/starRC/nanotime tools
Knowledgeof FPGA architectures. Knowledge of complex blocks like IO's, DDR's, PLL's is adefinite plus.
Knowledgeof timing characterization for advanced nodes in asic/structured-asics withvariability modeling
Workingknowledge EDA tools flow.
Experience: At least 6 years of industryexperience.
Education: Masters or higher
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