Senior ASIC Design Engineer
OmniVision Technologies - Santa Clara, CA

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The candidate will join a team of highly competent ASIC designers involved in the design, verification, and implementation (ASIC) of advanced platform for OmniVision’s future generation multi-media products.

Responsibilities:

Primary (70%)
• Provide detailed block-level RTL design and document
• Develop and execute thorough block level simulation and verification plan
• Participate in the FPGA platform development and lab debugging
• Generate script to facilitate work process
Secondary (30%)
• Participate in block level architecture design
• Assist embedded FW development
• Maintain IP and legacy modules
Requirements:

  • MSEE/CE with 3+ years of industry experience (or BSEE with 6 years working experiences)
  • Strong analytical, and problem solving skills, as well as hands-on lab debugging skills
  • Good knowledge of RTL coding, simulation and synthesis. Knowledge of design for low power and design for manufacturing
  • Able to write C/C++ code to model RTL blocks for simulation and verification
  • Able to write reusable Verilog RTL codes, follow design and DFT guidelines
  • Able to write verification test plans, and be able to run synthesis, static timing analysis, formal verification
  • Knowledge in languages relevant to the ASIC development process including Verilog, Unix Scripting, Perl, and Tcl
  • ISP function implementation experience is a plus
  • Self-motivated, excellent communication skills and ability to excel in a team environment.

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