To work, as a member of a team, on the representation and manipulation
of a logical netlist, which is linked to physical data, that serves
both logic synthesis and place-and-route. The candidate should be
knowledgeable about Verilog, ECO, DEF/LEF, physical-data representation;
be a quick self learner; and be able to tackle challenging technical
issues and work comfortably with legacy code. Experience working on
both a logic synthesis tool and a place-and-route system a plus.
Master's degree or above required
5+ years experience developing relevant EDA tools and C/C++ coding
Strong written and oral communication skills needed
Cadence is the global leader in software, hardware, and services that is driving the transformation of the electronic design automation (EDA) industry. This application-driven approach for creating, integrating, and optimizing designs helps customers realize Analog & Digital ICs , System-On-Chip devices, IP and complete systems at lower costs and with higher quality.
Cadence is an equal opportunity employer and is committed to hiring a diverse workforce.
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