Senior Engineer
Marvell 8 reviews - Bloomington, MN

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BSEE/MSEE with 4+ years of Digital/ASIC design experience with state-of-the-art design tools. (Synopsys preferred.) (MSEE counts as 2 years experience.)
Must be familiar with:
• DFT, Scan and ATPG.
• Static Timing analysis.
• HDL behavioral and RTL coding, Verilog preferred.
• Logic synthesis.
• Perl/TCL/shell scripts.
• High speed serial interface like Serial ATA, Serial Attached SCSI or Fibre Channel Preferred.
Perform various design tasks for system-on-chip (SoC) products using state-of-the-art IC design methodologies and design flows (Synopsys). Responsibilities will include Design for Test (DFT), test pattern development, static timing analysis (STA) using PrimeTime, synthesis support, placement and layout support. Other duties include RTL design, chip integration, and functional verification of design.
Engineering - Hardware
Digital IC Design

About this company
8 reviews
Thou marvell'st at my words, but be thee still; Marvell Technology Group offers digital and mixed-signal integrated circuits for data...