This position is for a senior-level candidate responsible for the development, architecture definition and maintenance of physical implementation EDA tools for FPGAs. In particular, the candidate will work on enhancing the delay calculation engine used in all aspects of physical design including physical synthesis, placement, routing, and timing analysis. Enhancements include identifying and implementing innovative new algorithms for improving the accuracy of pre-routing delay estimates, optimizing for memory and runtime, and creating efficient data structures to represent next generation FPGA routing hardware architectures.
- MS/PhD in EE or Computer Science with 3-5 years of experience, preferably in the EDA/Semiconductor industry
- Knowledge of algorithm for delay calculation would be preferred.
- Strong software engineering skills including extensive experience with C++
- Deep familiarity with object-oriented design concepts and software algorithms
- Good interpersonal skills
- Ability to collaborate effectively and seamlessly with different engineering teams
- Able to communicate technical concepts clearly and succinctly
Applicants are treated throughout the employment process without regard to race, color, religion, national origin, citizenship, age, sex, marital status, ancestry, physical or mental disability, veteran status or sexual orientation. The information requested here is not gathered for employment decisions. It is used only for compliance with Federal laws. Your responses are strictly voluntary, and any information provided will remain confidential. If you choose not to "self-identify", you will not be subject to any adverse treatment.