Microsemi Corporation (Nasdaq: MSCC) is a diverse power management semiconductor company with our largest commercial products division located in Garden Grove in Orange County, California. Our company specializes in system-engineered integrated circuits and high reliability discrete devices that support Blue Chip customers that are leaders in their fields. Microsemi has a long history of profitability, improving margins, and a strong balance sheet with a plan that includes investing in new facilities internationally.
The Senior Yield Enhancement Test Engineer is responsible for a variety of important and diverse work. Below are some of the highlights of the main responsibilities and duties:
- Yield improvement, monitoring and analyzing production data, identifying low yield issues, and initiate actions to improve product yield. Lead the efforts to resolve test related issues.
- Yield improvement thru optimization of test conditions and setup. Optimizing test conditions over test environmental and electrical conditions at Subcons.
- Work closely with subcon engineers to address various test related issues to ensure good yields.
- Work closely with TE/PE, R&D Team, Wafer Fab, Assembly vendors to collect data, identify root cause of yield issues and coordinate with the appropriate team to drive corrective actions and closures.
- Work closely with R&D Test, Design, and Systems Engineers, wafer Foundries, and Quality Engineering to support new product introduction and ramp up at offshore subcons.
Microsemi Inc. is an equal opportunity employer and does not discriminate on the basis of race, religion, national origin, sex, sexual orientation, age, physical or mental disability, marital status, or status as a disabled veteran.
- BSEE from an accredited institution, or equivalent. A masters degree in the related field is desirable.
- Minimum of 8 years of recent "hands-on" experience in Test or Product Engineering in a semiconductor company with 5 years of test development (HW/SW) of analog/mixed signal semiconductor products at both wafer probe and final test.
- Strong data analysis skills, understanding stdf format, experiences on data Conductor. Perl programming is a plus.
- Strong diagnostic skills to resolve yield issues with the following capabilities:
- Bench vs ATE data correlation; Repeatability and yield analysis; Package shift and guard-band limits analysis.
- Experience in applying and understanding statistical process control (SPC) and capability analysis (CPK) to analyze data.
- Must be familiar with and have a minimum of 3 years experience using at least two of the following testers:
- ASL 1000; Eagle ETS-300/364B; MicroFlex is a strong plus.
- OR experience and understanding of similar semiconductor testers.
- Proficient "hands on" knowledge and skills in using standard lab equipment for evaluation and correlation; including: Power supplies (Hewlett Packard Model 34401A, Keithley Source Meter Model 24400, Oscilloscopes (Tektronix Model TDS 3054B).
- Effective verbal and written English skills with ability to prepare and present written data reports and present results to R&D and Operations team members.
- Ability to use computer with working knowledge of Microsoft suite of tools (Word, Excel, PowerPoint, Outlook).
- Must be able to travel internationally and within the US up to 10% of the time.
- Must have the legal right to work in the United States.
- For ITAR purposes, must be US Person (US citizen or permanent resident)