Title: Staff ASIC Validation Engineer Location: Sunnyvle, CA 94089 Salary: Open and flexible depending on experience Bonus Eligible: Yes Benefits: World-Class benefits package Experience: 8+ years Brief Description Key member of ASIC design group. Expected to develop chip and/or module level specification, architecture, micro-architecture, Verilog RTL design, module verification and synthesis of relevant modules. Expected to trade off design complexity with timing and power. Expected to assist in timing closure of the chip and/or blocks and other responsibilities of ASIC design and lab validation Description Responsibilities: * Responsible for architecture and micro-architecture of complex ASICs and/or complex modules in ASICs * Work closely with System Architecture for ASIC specification and architecture * Responsible for complex module RTL coding and top level integration * Work closely with backend team from Synthesis to Tapeout process * Work closely with Silicon Validation and System Integration teams to bringup the chip and system Requirements: * Candidate's must have a Bachelor's Degree or higher in EE with very good academics.
Master's degree preferred. * 8+ years of experience in ASIC Design. * Solid knowledge and experience in RTL/Synthesis based ASIC design methodology and tools * Solid in logic design skills (micro-architecture development and implementation). * Experienced in STA and timing closure * Networking and packet based protocol experience is desired * Experience in packet or hybrid systems is preferred * Must have good communication skills * Must have ability and desire to work as a team Please forward resumes to greg (at) hirefighters.com.
I will call qualified candidates immediately to tell them more about this company and opportunity.
ITsaNetwork - 13 months ago
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