Staff Layout Designer
Arm Ltd - San Jose, CA

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Background

ARM offers IC designers a wide range of choices from its broad portfolio of Artisan memory products. The Artisan high-performance, high-density, low-power and ultra low-power memory generators are optimized for each silicon technology. ARM's Design Methodology includes comprehensive QA and validation procedures that can enable accurate designs with high manufacturing yields. ARM memory products have been used in circuits running as fast as 1GHz+ and are in production or development at 250nm, 180nm, 150nm, 130nm, 90nm, 65nm, 45nmand 32nm semiconductor processes for various foundries and IDMs. Our memory group comprises some of the industry’s leading experts in deep submicron circuit design and design for manufacturing (DFM) techniques. This position is a rare opportunity for a digital layout professional to work with the world’s most successful circuit and layout team with exposure to a wide variety of design rules from leading edge foundries. Candidate will organize, plan and guide a team of layout designers in a fast paced environment creating layouts for memory compilers in parallel, meeting project deadlines, while using the latest process technologies of 28nm, 20nm, 16nm, and 14nm.

Role
A candidate will be responsible for these tasks:
• Individual layout contributor as well as line management responsibilities
• Effectively lead/facilitate cross-functional teams, build cross-functional relationships, and develop cross-functional understanding in a high paced, rapidly changing environment.
• Able to lead multiple projects within different process nodes simultaneously
• Collaborate with circuit and layout teams to create project schedules
• Evaluate design rule tradeoffs for IC manufacturers (foundries and IDMs)
• Experiment and evaluate new layout architectures
• Contribute in layout procedures and techniques
• Ensure high quality, high performance in memory layouts
• Work with other layout resources to continually define, improve and develop layout infrastructure and methods
• Oversee other designers in projects including floor-planning, layout and verification.
• Teach and mentor other layout designers in high speed digital design.
• Utilizing advanced CAD tools, mask design knowledge to layout correct and robust physical design representation of circuits.
Personal Requirements
• College degree or Graduate from layout technical school

Job Requirements

Essential Technical Skills

• 10 years layout experience drawing memory compilers with good knowledge of hierarchical layout planning
• Layout experience with deep submicron technologies (20nm or smaller)
• Demonstrable experience managing direct reports in a high paced environment
• Fundamental understanding of Design For Manufacturability (DFM) layout techniques
• Familiarity with Cadence Virtuoso (DFII, Opus) layout environment
• Must have good understanding on layout optimization, core-array development, physical verification and reliability checks at leaf-cell level and instance level.
• Able to independently address EM/IR issues and fix layout accordingly
• Ability to accurately plan and schedule responsibilities
• Demonstrable scripting/automation capabilities to improve productivity

Desirable Skills

• Experience working with place & route chip design tools
• Programming or scripting experience
• Reading and understanding DRC/LVS run sets
• Experience managing direct reports in a high paced environment

Personal Skills

• Enthusiastic, self-motivated, flexible with strong inter-personal skills
• High degree of initiative
• Willingness and ability to contribute to process improvement initiatives
• Demonstrate a positive attitude and respect for all members of the team
• Demonstrate excellent leadership and communication skills and teamwork

Package

ARM will offer the following benefits for this position:
• Salary - Commensurate with experience
• Stock
• Medical Insurance
• Dental Insurance
• Life Insurance
• Contributory 401K
• 4 weeks paid vacation

Arm Ltd - 14 months ago - save job - block
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