Staff Logic Design Engineer
Marvell - Santa Clara, CA

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MS + 5yrs

Description:
Main Responsibilities:
+ Help develop ARM based SoC for Mobile Communication.
+ Help integrate multi-ARM core, AXI based SoC
+ Development will be done using Verilog/System Verilog, including FPGA based prototyping
+ Leading Edge sub-micron ASIC design flow, including Verilog, Linting, Simulation,
Synthesis, DFT, Static Timing Analysis, Timing closure
+ Interface with design, verification, and PnR teams
+ Develop, implement, and verify Chip level power-management schemes

Desired Qualifications:
+ Self Motivated, Team Player that can work with various groups
+ Ability to multi-task various Design activities.
+ MS in Electrical Engineering required, 5+ years in ASIC Design.
+ Strong knowledge of ARM, AXI, DMA SoC architectures
+ Familiar with peripheral devices like I2C, SDIO, USB, SDRAM, USIM
+
+ Prior experience in integrating digital modems, GSM/GPS/CDMA, Ethernet
Physical Layer or other communication systems would be helpful
+ Should be comfortable with developing/modifying C/C++, Shell scripting, Perl, and Makefiles

Profession:
Engineering - Hardware

Discipline:
Digital IC Design

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Thou marvell'st at my words, but be thee still; Marvell Technology Group offers digital and mixed-signal integrated circuits for data...