This position is responsible for architecting critical components of DDR Design IP verification environment using a SystemVerilog-based coverage-driven verification methodology. Typical activities in this role include development of testbench environment, creation of test plans from design specifications, defining and implementing a coverage plan, writing and constraining tests for achieving coverage goals. The candidate will also be expected to support the scripts used in the verification environment, debug regressions, manage automated verification processes, and support customer delivery efforts.
Principals only, no agency or search referrals will be accepted.
- 8 - 15 years of experience.
- Prior experience architecting verification testbenches
- Strong multi-tasker, fast learner with high productivity
- Prior detailed work experience with coverage-driven verification with SystemVerilog, Testbuilder C++ or other Hardware Verification Languages
- Experience with writing comprehensive test plans, developing coverage models, writing tests and closing on feature verification
- Knowledge of DDR protocol and AMBA bus fabrics a plus
- Strong written and oral communication skills
Cadence is the global leader in software, hardware, and services that is driving the transformation of the electronic design automation (EDA) industry. This application-driven approach for creating, integrating, and optimizing designs helps customers realize Analog & Digital ICs , System-On-Chip devices, IP and complete systems at lower costs and with higher quality.
Cadence is an equal opportunity employer and is committed to hiring a diverse workforce.
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