Senior Asic Timing Engineer jobs in Santa Clara, CA
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SMTS - FPGA Design Engineer
Altera Corp.
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San Jose, CA
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STA, and Timing closure in FPGA/SOC/ASIC Experience... ASIC Development Flow integration,RTL coding in Verilog and or SystemVerilog, Synthesis, STA, and Timing...
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Sponsored by Dice - 5 days ago
Advanced Micro Devices, Inc.
77 reviews
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Sunnyvale, CA
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Specification of key functional blocks of the chip set. Design and implement the functional blocks, using Verilog.....
8 days ago
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Esencia Technologies, Inc.
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San Jose, CA 95131 (North Valley area)
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Experience in developing and supporting a fully automated STA scripts/flows using Synopsys PrimeTime. Strong written / verbal communication skills are a must,...
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25 days ago
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Microsemi
5 reviews
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San Jose, CA
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BS or MS in Electrical Engineering or Computer Engineering. Key tools include Synopsys Design Compiler, Formality, Primetime, Galaxy Constraint Audits, and...
8 days ago
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Marvell
3 reviews
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Santa Clara, CA
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Self Motivated, Team Player that can work with various groups. Excellent knowledge of Verilog, SystemVerilog, C++, Perl, Makefiles....
25 days ago
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Omnivision Technologies
4 reviews
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Santa Clara, CA 95050
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1. MSEE/CE with 3+ years of industry experience (or BS EE with 6 years working experiences). Knowledge of design for low power and design for manufacturing....
Monster - 1 day ago
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Nvidia
13 reviews
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Santa Clara, CA
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Expertise in analyzing and converging on crosstalk delay, noise glitch, and electrical rules in deep-sub micron processes required....
Monster - 23 days ago
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Marvell
3 reviews
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Santa Clara, CA
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Static Timing Analysis & Timing closure. Verification & debugging with digital simulator. DFT, test compression, ATPG & ATE testing....
30+ days ago
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Apache Design Solutions, Inc.
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San Jose, CA
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Assist customers in running Apache design and verification tools and simulators. Develop utilities for troubleshooting and debugging problems utilizing...
14 hours ago
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ANSYS
4 reviews
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San Jose, CA
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Assist customers in running Apache design and verification tools and simulators. Develop utilities for troubleshooting and debugging problems utilizing...
14 hours ago
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Synopsys
8 reviews
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Mountain View, CA
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Some occasional travel is required. Background in related signoff methodologies such as HSPICE simulation, delay calculation, multi-voltage designs, and IR drop...
30+ days ago
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ASIC Static Timing Analysis Engineer (ESE13-0103-1)
Esencia Technologies, Inc.
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San Jose, CA
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plus Responsibilities As a senior member of ASIC/SoC design team, you’ll be responsible for full chip timing constraints development, full chip Static Timing...
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Sponsored by Esencia Technologies, Inc. - 25 days ago
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