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Data Center Solution Engineer

Data Center Solution Engineer - DELL CORPORATION

Austin, TX


Work Experience

Data Center Solution Engineer


2012 to Present (4 years, 6 months)

Working on platform related issues specific to multiple accounts. 
• Driving ODMs for any platform related issues as well as new requirements to be implemented 
• Performing Functional Validations for any new configs provided by customer 
• (Specint benchmark test, Power test(entek and spec power) Iperf network performance testing for 1g and 10g loms))memory performance testing(google, russion etc..).Storage testing for • 3g and 6g sas and sata.(grind7) 
• Deployment of e-sample(Engineering samples) to the customer Data Centers 
• Resolving any hot issues onsite at the Customer Data Centers 
• Troubleshoot any issues seen by Rack Infrastructure companies 
• Troubleshoot the systems(Servers ) for customer issues.This might involve Signal integrity issues

Validation/SI Engineer

IBM Corporation

2008 to 2012 (4 years)

Worked on DDR2/DDR3 Interfaces 
• Worked on DDR memory development on mid range Servers 
• Responsible for reviewing and simulating results, checking for design guidelines and overseen characterization, validation and testing 
• Utilize Perl automation and Linux 
• Familiar with I/O architecture as well as margins 
• Job responsibilities include evaluating memory performance and characteristics, validation across process, voltage and temperature (corner testing) 
• Board level/ bring-up, debug, and verification of the memory interface 
• High speed bus signal integrity debug/characterization 
• Analyzing, troubleshooting, and recommending solutions to optimize memory interface performance 
• Take ownership of the memory interface from bring up and after • Documenting characterization and validation results 
• Worked on PLL issues and memory clock problems, mainly jitter problems 
• Performed jitter analysis, jitter measurements and problem solving 
• Worked with different departments on resolving issues 
• Utilized tools such as oscilloscopes, logic analyzers, etc. 
• Supporting overseas IBM functions and providing training for them.(IBM India) 
• Having regular interlock meetings with TDC(Taiwan Design Center), China design center.

Product Development / Signal Integrity Engineer/System Validation


2000 to 2008 (8 years)

Create strategies and validation techniques for electrical subsystems 
• Responsible for creation of validation techniques for PC subsystems 
• Electrical Validation of High speed interfaces such as Serial ATA (1.5,3.0,6.0)&SAS Fully Buffered DIMM (FBD) PCI-Express (Gen1, Gen2), DDR2, DDR3, FSB, CSI(QPI).and USB 2.0.&1.1, FSB, Gigabit Ethernet 
• Worked on static and dynamic power testing 
• Coordinates analog validation efforts from various teams including architects, Design Engineers, simulation, Tester and System Margining validation engineer's 
• Work with Audio verification 
• Experience with ADC, DAC 
• Developed expertise in developing test plans and executing test plans 
• Developed excellent debugging and problem solving ability 
• Developed advanced knowledge in the use of state-of-the-art lab equipments such as High bandwidth oscilloscope, Bit Error Ratio Tester (BERT), Time Domain Reflectometry (TDRs) and Vector Network Analyzer (VNAs) 
• Utilized Allegro Cadence in the design of Dell servers, Blades, work-stations, and Notebooks which included all internal hardware (i.e. PCB's, storage cards, video cards, and motherboards.) 
• Duties included all activities necessary to take a product design from concept to production, schematic design, and attending to EMC issues working with Development Engineers and ECAD to do electrical analysis. 
• Involved in all phases of high speed system/board design including I/O design, clocking, signal integrity, noise margin, test and verification. 
• Familiar with JTAG protocol. 
• Used Hspice, worked with board constraints and stackups. 
• Knowledgeable of RF concepts; transmission lines; s-parameter models, etc. 
• Proficiency on field-solver and channel simulators from ADS, An soft, HSpice 
• Performed PCB timing analysis, work with board engineers and layout designers to implement all SI rules, develop layout/SI checklists. 
• Working knowledge of design tools: HSPICE or SPICE-like simulators, schematic/layout entry tools 
• Worked with the OEM vendors (outsourced engineering teams) and Dell Taiwan team to • ensure that their design meets INTEL requirements for the processor bus, system clocks, and 
• High speed busses by checking their design rules and sending them feedback to make the • corrections 
• The process involves participating in design reviews, providing feedback, interacting with other SI engineers and providing design/SI feedback to the design team 
• Performed Signal Integrity analysis on High Speed Analog Computer Bus Technologies at the System level on several Motherboard designs 
• Developed company wide EA (electrical analysis) test plans, incorporating test point for validation 
• Drive resolution of signal integrity issues impacting assigned technologies

Test Supervisor

IBM Corporation

1990 to 2000 (10 years)

Manage group of technicians to support the manufacturing lines 
• Wrote programs and order fixtures for ICT test 
• Worked with design engineers for Power PC products 
• Troubleshoot and Repair systems to the component level and failure analysis (RISC6000) 
• Responsible for optical test programming/maintenance

Inspection Supervisor/Test Engineer

Eagle Signal Corp

1986 to 1990 (4 years)

Supervised technicians for incoming product test verification, testability, quality control and assurance.

Design/Test Engineer

MCC Corporation

1984 to 1986 (2 years)

Performed inner and outer lead bond verification and integrity for proto-type microelectronics substrates 
• Maintaining, scheduling and operating Wafer equipment for tape automated bonding production, 
• Performed leakage current test and Dielectric test on beam tapes 
• Performed above task used RF impedance analyzer, Keithley test equipment, probe stations 
• Trained on ATE equipment such as ESP-7700 continuity tester for testing chip on tape 
• Developed co-axial probe card design for controlled impedance testing

Engineering Technician Supervisor


1981 to 1984 (3 years)

Supervise technician to support manufacturing operation and customer returns, Proto-type development


AA in Engineering

Sac. City College


Pacific University


signal integrity,functional testing,hardware development,bring up

Additional Information

CAE Tools: Cadence (Allegro, Spectraquest, Sig Explorer), Apsim (Aspice), Hspice, Pspice, ADS 
Software Programming Languages: Basic, C, Mat lab 
Hardware Language: VLSI CMOS Design, Logic Design Analysis, Digital Circuit Design and Analysis 
Operation Systems: UNIX, Windows (NT, 98, 95, 2000, XP), Server […] 
Additional Classes: Design of experiment, Root cause Analysis, Basic Statistics with JMP software