Swapnil Agarwal

Digital Design Engineer

October 2008 to May 2012

Paris, France
Project SQN3210 [LTE SS]
➢ Creating new module for LTE Uplink-datapath to implement improved clocking scheme
➢ Removed WiMax logic from SQN3110
➢ Bug fixing and verification

Project SQN3110 [LTE + WiMax SS]
➢ Development and verification of Low Power Controller (Lpctrl) module
• Study of the low-power features of the chip
• RTL development of the module
• Created list of Always-on memories and retention flip-flops
• Verified Cadence INCISIV low-power simulation parameters and modified VHDL modules for low-power simulation. Interacted with Cadence support to find solutions
• Created scenarios to test the low-power mode and clock-gating scheme
• Added SystemVerilog properties and run regressions for property and functional coverage
• Gate level and Back-annotated simulation
• Written Lpctrl ASIC specifications and verification plan
• Supported Platform Integration and Software teams to verify Lpctrl module on FPGA and in final chip

➢ Platform verification
• Verification of platform scenarios in ASIC and FPGA mode
• Written Platform ASIC specifications

➢ Interrupt handling optimization
• Updated RTL by removing external interrupt handler and associated memories
• Modified Lattice MICO assembly code and interrupt handling functions
• Verified MICO scenarios in ASIC and FPGA modes

➢ LTE DSP arbitration verification

➢ Replacing ARM by MIPS
• Studied about MIPS Data and Instruction cache memory organization, interrupt scheme, shadow registers and Resets
• Replaced ARM946 by MIPS14Kc
• Studied about MIPS24Kc OCP interface and MIPS OCP-to-AHB bridge
• Later replaced MIPS14Kc by MIPS24Kc for good synthesis result

➢ WiMax Macro
• Removed platform from SQN1310 to create WiMax core for SQN3110, which uses LTE platform
• Instantiated wimax_macro inside SQN3110 core and verified through WiMax Marbiter tests

➢ LTE and WiMax Clock generation
• Created new modules wimax_clkgen and lte_clkgen and instantiated them inside wimax_macro and lte_top respectively to separate LTE and WiMax hierarchy

➢ Bug fixing and verification
Project SQN3010A [LTE SS]
➢ Design cpu_platform2lte module as a bridge between LTE platform and LTE Datapath
➢ Optimized Lattice IP to make Shift, Compare and Multiplication command execute in 1-cycle
➢ SystemC checkers for LTE Downlink datapath modules
➢ Platform verification (UART, WDT, USIM, SPI, Interrupt, Inter CPU and SDRAM scenarios)
➢ APB master scenario (Verified different masters' accesses to different memories)
➢ Verification plan and ASIC specifications for downlink datapath modules
➢ Regression for code-coverage
➢ Bug fixing and verification

Project SQN1310 [WiMax SS]
➢ Platform Cleanup (Removing Client CPU and associated UART, WDT and TIMERS)
➢ Platform regression debug in ASIC and FPGA mode
➢ Written ASIC specifications
➢ Bug fixing and verification

Project SQN2130A [WiMax BS]
➢ FEC Block Bank update
• Design RTL modules to convert the stream of LLRs into SUBCARRIER and to re-convert the SUBCARRIER into the stream of LLRs
➢ Update and verify Top-level testbench
➢ Fixed PHYBE bugs and written verification plan
➢ Written PHYFE verification plan

Others
➢ Cadence C2S evaluation
➢ Mentor Graphics' Catapult evaluation