Seeking a position in an academic research environment, where there is an opportunity to exhibit strengths and enhance skills while striving for the growth and development of the company
June 2010 to July 2012
• Responsible for evaluation of semiconductor devices and components.
• Develop testing protocols, prepare equipment, document test results and maintain records for later analysis.
• Other duties include preventative maintenance, maintenance of testing equipment and overseeing the inventory of validation supplies.
• The design of chip , layout circuit design, circuit checking, device evaluation and characterization, documentation of specifications, prototype construction and checkout, modification and evaluation of semiconductor devices and components
Masters in Electrical and Computer Engineering
2012 to 2014
BTech in Electrical & Electronics Engineering
Master's in Science
. As a graduating Electrical/Computer engineer graduate student at The University of Illinois at Chicago my academic background, coupled with my relevant work experience, has given me the tools and ability necessary to add value to the position, and ultimately your organization.My interest in Computer Engineering is long standing and my well-rounded background makes me an excellent candidate for the Electrical Engineering position. I had a past experience of 2 years with IBM as a Validation Engineer where my job responsibilities includes The design of chip , layout circuit design, circuit checking, device evaluation and characterization, documentation of specifications, prototype construction and checkout, modification and evaluation of semiconductor devices and components . As a sophomore, I served as Treasurer on the Student Council and played varsity tennis. In my junior year, I attained a position in the Student Services Office where I received first-hand experience in organization, teamwork, and responsibility. I have earned several awards while a student at UIC, was awarded the prestigious merit scholarship for excellence in academics for 1 year in UIC ,Chicago, USA.Awarded a sum INR 50000 for first prize Golden Challenges in Performance Optimization in Chips using VLSI, conducted at IIT Bombay, Jan 2009.Awarded first prize for Chip modeling at International Conference conducted by Clean Tech India conference at VIT University and Dean's List in the Fall of 2012. Please find my attached résumé, which provides full details of my qualification. Feel free to contact me at (312) […] or email@example.com for any following up purposes. I appreciate your consideration and look forward to further discussing the Electrical/Computer Engineering opportunity with you.
Logic Analyzers, Function Generators, Oscilloscopes (Agilent/Tektronix), Spectres, Digital Communications Analyzer
Programming Languages C, C++, Perl, Assembly level programming in 8085, 8051, Shell Scripting, VHDL(Hardware Descriptive Language), Verilog
Operating Platforms MS Windows, Mac, Linux (Redhat and Ubuntu), Android
Analog and Mixed VLSI, Intro to VLSI, Digital System and Designs, CAD on Digital Systems, Analog Integrated Circuits, Wireless Communication, Design and Testing of Digital Systems and their Reliability characteristics.
• Designing Low Cost inverter and optimizing results using Pspice and MATLAB. ( July 2008- January 2009)
• Optimization On load flow analysis using Algorithms like Particle Swarm Optimization and Ant Algorithm For Discrete Optimization. (October 2009- May 2010)
• Design Block Cipher (RC6) Encryption Phase using VHDL and Quartus 9.1 sp2 Web Edition
• Design of 5-stage Voltage Controlled Ring Oscillator with MOSFET in MOSIS AMI05 process. The transient simulations were done in Cadence and a comparison was made with the theoretical calculations (Sept ‘11- Dec ‘11).
• Design of 8-bit slice ALU data path in both behavioral and structural modeling approaches using VHDL and Quartus9.1 for simulations. The ALU was then integrated with a register set to constitute a datapath (Dec ’12- Jan’13).
• A system has been designed and implemented for the Bus administrator. In this system a bus Administrator can Change the details, number of seats in a bus, their routes and number of buses in a route etc This computerized system enables the administrator to increase his business efficiency in terms of profits and can cut manual labor. Errors can be minimized and cannot have a chance of issuing the same ticket to many. (January 2009- May 2009)
• ATPG (Automated Test Pattern Generation (Deterministic Approach)and Pseudo Random Test Vector Generation Methods(Psuedo Random approach) on 11 ISCAS85 Benchmarks. Generated ATPG vectors in AtalantaM2.0.for 11 ISCAS85 benchmarks. Ran simulations to compare and analyze fault coverage of each set of test vectors. Produced documentation for all verification and simulation results. Generated Random vector by using MISR(Multiple Input Shift Registers) in PerlScript […]
• Audio Amplifier Project: using LM386 IC Designed 2 channel stereo audio amplifier with digital volume control and simulated the results using HSpice […]