Seeking a position to utilize my skills and abilities that offers professional growth while being resourceful, innovative and flexible
December 2010 to February 2011
Bachelor of Engineering in Electronics and Communication Engineering
➢ Good understanding of the ASIC and FPGA design flow
➢ Experience in writing RTL models in Verilog HDL and
Test benches in SystemVerilog
➢ Very good knowledge in verification methodologies
➢ Experience in using industry standard EDA tools for the front-end design and verification
➢ Indian Institute of VLSI Design and Training certified VLSI Design course from Indian Institute of VLSI Design and Training Centre, Bangalore
➢ Maven Silicon Certified Advanced VLSI Design and Verification course from Maven Silicon VLSI Design and Training Center, Bangalore
Dedication, Hard Working Nature, self motivated
Mini Project: Digital Alarm Clock - RTL design and Verification
HVL: System Verilog EDA Tools: Modelsim, Questa - Verification Platform and ISE
➢ Architected the design
➢ Implemented the RTL using Verilog HDL
➢ Verified the RTL using Verilog HDL and System Verilog
➢ Implemented the design on the Spartan, Xilinx FPGA and verified the design on the board
Dual Port RAM -Design and verification
HVL: System Verilog
EDA Tools: Modelsim, Questa - Verification Platform and ISE
➢ Implemented the Dual Port Ram using Verilog HDL independently.
➢ Architected the class based verification environment using system Verilog.
➢ Verified the RTL module using System Verilog
Generated functional and code coverage for the RTL verification.
Digital Design of 8-bit RISC processor for embedded application
EDA Tools: Cadence: - NCVerilog, Simvision, RTL Compiler, SOC Encounter.
The aim of the project is to design an 8-bit RISC processor based on PIC16C57 from Microchip. RISC stands for Reduced Instruction Set Computer which as the name suggest have simple (rather than a complex) instructions to enable faster instruction decoding to provide higher performance.
The RISC architecture uses only 33 single word/ single cycle instructions. All instructions are single cycle except for program branches which take two cycles. The easy to use and easy to remember instruction set reduces development time significantly.
➢ Implemented the RTL using Verilog HDL.
➢ Verified the RTL using Verilog HDL.