What is the average salary for jobs related to "senior uvm asic design verification engineer"?
The average salary for "senior uvm asic design verification engineer" ranges from approximately $112,343 per year for Senior Design Engineer to $150,049 per year for Senior Staff Engineer.
Salary information comes from 191 data points collected directly from employees, users, and past and present job advertisements on Indeed in the past 12 months.
Please note that all salary figures are approximations based upon third party submissions to Indeed. These figures are given to the Indeed users for the purpose of generalized comparison only. Minimum wage may differ by jurisdiction and you should consult the employer for actual salary figures.
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