Senior Packaging Engineer
In this position, you will be joining the IDGa SOC design team to work on signal and power integrity for SOC products for phones and tablets. You will be accountable for the package's path-finding, definition, development, and PRQ.
Responsibilities include but are not limited to:
- Work independently to define and ensure optimal and efficient overall package solution, under one umbrella, by leading, partnering and influencing both external, cross-site and internal multi-disciplined teams including:
O Platform architects to define package footprint, pin maps, optimized quadranting, mechanicals and system floor plan definition
O Platform groups on design of platform motherboard,
O Assembly Test Technology Development (ATTD), Assembly Test Manufacturing (ATM) package technology, package form factor, Z-height, layer thickness, bump pitch and heat spreading solutions including path-finding.
O KIT and HIP teams IP development
O Package Design owners on Package optimization and tradeoffs, on Package Layout quality for Signal Integrity and Power Delivery, KIT team.
O Assembly Technology Development Quality and Reliability (ATD Q&R) on reliability
O Architects and Planners on schedule, features and landing zone (LZ).
O Si IDGa design floor-planning on cost reduction, placement and performance.
O Interface with vendors.
- Develop routing guidelines for the power delivery network on package and on the motherboard.
- Drive optimal overall tradeoffs of cost, schedule, performance, power delivery and reliability.
- Lead communication and negotiation between all stake holders by chair/co-chair package development meeting (CPIWG) and representing project in all package related meetings.
- Document requirements for package mechanical, signal integrity and power delivery attributes (PDRD).
- Work closely with lab and perform lab measurements to validate the robustness of the power delivery network design and perform debug activities associated with it.
- Lead the design of Package Test Vehicles (TV).
You should have sound background knowledge of analog modeling of parasitics, droop, Z'f', noise, and eye diagrams, as well as a strong experimental and modeling background. You should also possess good knowledge on basic Statistical Process Control (SPC) and/or Design of Experiments (DOE) principles. It is also beneficial to have knowledge of electrical field theories and electronic fundamentals, analog signaling behavior, circuit analysis, power delivery network modeling, electromagnetics, and/or applied materials and physics.
The ideal candidate should exhibit behavioral traits that indicate:
- Ability to analyze data and accurately communicate results, risks and recommendations
- Ability to work in groups and across disciplines.
- Strong verbal and written communication skills.
- Good leadership skills.
- A positive, can-do attitude.
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
- BS + 6 yrs. exp.; MS + 4 yrs. exp.; PhD + 2 yrs. exp. in Electrical Engineering, Applied Physics, Materials Science, Mechanical Engineering, Chemical Engineering, or related discipline
6+ years of experience in package design, including:
- High-speed interfaces, I/O buffer models, package parasitic extraction and models, power and/or ground plane modeling.
- PKG Layout, die and board requirements for layer stack-up
- Power Delivery, Power Integrity and Signal Integrity
- Package technology electrical and mechanical design rules
- Package technologies: Co-PoP, BBUL, MCP, Coreless, TSV, Fast_WIO, LC filters, Dedicated quiet power rails, HIP encroachment, Small form Factors (SFF), Decaps.
- Test vehicle designs for metal interconnect and die-package process development for early analyses or establishing tradeoffs metrics in cost and performance
- Motherboard VR design requirements
7+ years of experience tools for Computer Aided Design (CAD) and/or Computer Aided Engineering (CAE), including at least 3 of the following categories:
- Mentor Graphics, Expedition and Cadence, Allegro Package Designer, FIELD
- Ansoft, HSpice, ANSys-Apache, Presto, Links
- Knowledge of linear and non-linear finite element analysis methods and tools, and commercial software such as ABAQUS or ANSYS
- Mathlab, JMP
- ICC, Genesys, Galaxy, Parade, Gallery, Safran, Netbatch
3+ years of experienced with DFx architecture (JTAG, BIST, Scan) and mixed signal testing of I/Os (DDR, PCIE, USB), and PLL/DLLs.
3+ years of experience or more with any of the following:
- CPU package designs
- CPU Si design
- I/O Bus designs
- Automated Tester Equipment
Apr 26, 2013
Employees in the Intel Architecture Group (IAG) deliver innovative platforms across computing and communication segments including data centers, mobile and desktop personal computers, handhelds, embedded devices and consumer electronics. Intel's industry leading technology is used to create integrated hardware and software solutions such as processors, chipsets, communication radios, graphics processors, motherboards, and networking components that deliver capabilities from security and manageability to computing performance and energy efficiency. IAG employees are at the forefront of enabling a new era of computing that is more integrated into all aspects of our daily lives.
Compute Component Development Organization (CCDO) is one of Intel's leading design groups. It has delivered and continues to design leading products, including CPU and SOC products in the mobile, desktop, and server segments. CCDO is an energetic and innovative design team with more than 20 years of experience in CPU design.
We will accept applications/resumes until 60 days after posting date or earlier at Intel's discretion
Intel - 11 months ago
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